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Advanced Detectors, Systems, & Nanoscience

Above: CMOS imagers during processing at the Microdevices Laboratory.

Custom Back-illumination Processes for High-Performance CMOS Imagers

Custom end-to-end post-fabrication processes employing JPL’s delta-doping technology were developed to produce back-illuminated high-performance CMOS and CCDs. A hybrid CMOS array designed at JPL (Cunningham et al., 389c), for example, requires hybridization to a thinned detector membrane. The capability to hybridize ultra thinned membranes to a readout array is a unique capability that is enabled using JPL’s delta-doping technology and thereby achieving high QE and low dark current in this CMOS array.

In collaboration with Rochester Institute of Technology and University of Rochester, we have embarked on development of back-illuminated, thinned, delta-doped CMOS imagers for planetary applications. These detectors are fabricated using shared foundry runs and die-level thinning was necessary. A new approach to thinning with higher throughput and good uniformity was devised.

 

Current Projects